1. Field of the Invention
The present invention relates to a wiring board on which bumps are formed and a method for manufacturing the same, and also relates to a semiconductor device using the wiring board.
2. Description of Related Art
A conventionally known semiconductor device has a semiconductor element that is face-down mounted on a wiring board provided with bumps and electrode pads on the semiconductor element are bonded to the bumps on the wiring board using a TAB (Tape Automated Bonding) method commonly used for the manufacture of semiconductor devices for liquid crystal displays etc. (see US 2004/0212969 A1, for example).
Hereinafter, a conventional wiring board provided with bumps, and a semiconductor device using such a wiring board will be described with reference to the drawings. FIG. 8 is a plan view showing a conventional wiring board 21, and FIG. 9 is a sectional view taken along the line B-B′ in FIG. 8.
In FIGS. 8 and 9, reference numeral 22 denotes an insulating base, and reference numeral 23 denotes conductor wirings formed on a surface of the insulating base 22. A bump 24 is formed on a leading end portion of each conductor wiring 23. Numeral 25 denotes first conductive layers for coating the surfaces of the conductor wirings 23 and the bumps 24, which are formed by electrolytic Au plating, electrolytic Ni/Au plating, or electroless Sn plating or the like.
In the wiring board to be used for packaging according to the TAB method, the insulating base etc. is formed of a flexible material or formed so as to have flexibility, and the steps of supplying the wiring board, mounting the semiconductor element on the wiring board, carrying out inspection after the semiconductor element has been mounted, etc. are performed continuously by a reel-to-reel method. In order to impart flexibility to the wiring board, a flexible tape formed of polyimide or the like and having a thickness of about 12 μm to about 40 μm is used as the insulating base 22. The conductor wirings 23 on the insulating base 22 are formed by patterning a Cu foil having a thickness of about 9 μm to about 18 μm by wet etching. In a case of forming the conductor wirings 23 through wet etching, since the etching proceeds from the upper faces of the conductor wirings downwards and in the transverse direction, the cross-section of each conductor wiring 23 is tapered as shown in FIG. 9. For example, in a case where the pitch of the conductor wirings is 40 μm, when a Cu foil of 9 μm in thickness is used and subjected to wet etching so that the bottom width of the conductor wiring 23 becomes 15 μm, the width of the upper face part of the conductor wiring 23 will be about 8 μm. Each bump 24 is formed by electrolytic copper plating so as to have a thickness of about 8 μm and a width of about 20 μm, crossing the longitudinal direction of each conductor wiring 23 over both side regions of the conductor wiring 23.
FIG. 10 is a sectional view showing a semiconductor device obtained by face-down mounting a semiconductor element 26 on the conventional wiring board 21, with application of heat and pressure. Electrode pads 27 are formed on the semiconductor element 26, and second conductive layers 28 are formed to coat the surfaces of the electrode pads 27. The second conductive layers 28 are bonded to the bumps 24 on the wiring board 21 via the first conductive layers 25. The second conductive layers 28 are formed by electrolytic Au plating, electroless Ni/Au plating or the like.
Recently, due to the tendency for larger and higher resolution liquid crystal display panels, the number of pins has increased in a semiconductor device used for a liquid crystal display assembled using the TAB method. In some usages, a semiconductor chip of about 20 mm×1 mm having more than 1000 electrode pads has appeared. As a result, the pitch for the electrode pads has been decreased, and a pitch of not more than 40 μm is required.
However, in a semiconductor device using the conventional wiring board 21 as shown in FIG. 10, only the bottom faces of the conductor wirings 23 adhere to the surface of the insulating base 22. The bottom faces of the bumps 25 grow in contact with the surface of the insulating base 22 due to the electroplating, but it does not adhere. Therefore, when the wiring width of the conductor wirings 23 is decreased corresponding to the narrowing pitch of the electrode pads 27, the adhesion strength between the conductor wirings 23 and the insulating base 22 will be decreased. This will cause a problem that the conductor wirings 23 are peeled from the insulating base 22 due to a thermal stress after the face-down mounting of the semiconductor element 26 or a mechanical stress caused by bending or the like of the wiring board 21 during a reel-to-reel conveyance that is characteristic to the TAB method.